The present invention relates to circuit boards and integrated circuit packages and, more particularly, to method for making electrical circuits on circuit board or integrated circuit packages.
Electroplating technology has been around for over 50 years, providing circuit board designers and fabricators a controlled, highly reliable, and cost effective means of applying a surface finish to the board. In most electroplating schemes, a power source (rectifier) is electrically connected to an anode bar that is in turn connected to either bars of the desired metal finish, or baskets containing balls or nuggets of the desired metal finish. The metal bars or nuggets provide a source for the metallic ions of the required finish. The source is then submersed in an electrolytic solution of a similar metallic nature that provides a conductive path for the ions. To an opposite bar, the cathode is attached to the negative or return path of the power source (rectifier). Electrically attached to the cathode is the work piece, or circuit board, that requires the plating deposit and in turn is also submersed in the conductive electrolytic solution. When a voltage is applied across the anode and cathode, the metal ions move from the solution to the cathode, and deposit on the work piece surface, and the ions in turn replenished by the anode source. Of course, in order to be electroplated, all circuit networks on the work surface (circuit board) must provide a continuous path to the cathode bar. Thus, any circuit not connected to this path will go un-plated. Electroplating technology is well understood by those skilled in the art and its methodologies are well documented.
For most printed circuit manufacturing flows utilizing electroplating technology, the circuit board is designed in such a way as to independently connect each electrical network on the circuit to an external bus bar that is then connected to a perimeter bus, which is then in turn connected to the cathode. Using this technique allows fabricators to form the circuit layer independently of considering future bussing requirements. Thus, in a typical flow, the circuit board is processed through an xe2x80x98etchingxe2x80x99 procedure that electrically isolates one network from the next, forming a functional circuit board. Since each network is independently connected to the bus, a protective coating such as soldermask can be applied over the entire circuit board without consideration for future bus requirements. In turn, a final finish can be electroplated onto the circuit (selectively applied onto areas where the soldermask is designed to be clear) by conventional electroplating described above. Once the electroplating operation is complete, the circuit card or board can be singulated from the panel, with each circuit network regaining its independence by mechanically cutting off the common bus, and thus becoming a functional circuit board. This technique is well understood by those skilled in the art.
When an electrical path is not available to all the circuit networks that require a surface finish, often a process known as electroless plating is used. In this method, the plating solution provides its own ions for deposit on the submersed work area. A variety of techniques are used to augment the metallic deposition process, including the use of catalysts, high temperature baths, and reducing agents. For some types of metallic deposits, the electroless technology used has proven very reliable. An example of this is the electroless copper process used to fabricate printed circuit boards. For metal surface finishes used in circuit board processes, however, the electroless methodologies have proved costly and unreliable. An example is the electroless deposit of nickel followed by the electroless deposit of gold in substrate integrated circuit (IC) packaging applications. These nickel deposits typically use phosphorous as a reducing agent that co-deposits along with the nickel and results in undesirable inter-metallic alloys when combined with eutectic solder. In addition, the electroless deposit of some metal finishes including nickel and gold takes considerably longer than deposits of the same metals using an electroplating technology. The transition to these electroless processes has been dictated primarily by geometric constraints imposed by the fine features typically found in very dense circuit boards including IC packages.
As circuit density increases, the number of available paths to xe2x80x98routexe2x80x99 or lay out the board in such a manner as to connect everything to the electrical bus becomes limited. Manufacturers are pushing towards miniaturization, which places routing room on a circuit board or substrate for IC packaging at a premium. For some designs operating at high frequencies, the need to bus is further compromised by the electrical performance of the circuit. The termination of a circuit network at a desired point is compromised by the need to connect the network to the electrical plating bus. This extension of the circuit line creates undesired attenuation in the circuit, which is especially noticeable in designs operating at speeds of over 500 Mhz. Often the reliability of electroplating technology is sacrificed to obtain the final electrical performance of the circuit.
Castro et al U.S. Pat. No. 6,107,683, issued Aug. 22, 2000 describes a process for making a ball grid array substrate package wherein a seed layer is formed by electroless plating of a seed layer that is used as a bussing mechanism to electrolytically form the circuit pattern. Nickel-gold plating 231A, 231B for the wire bond pads is applied electrolytically using by means of a conductive layer 218 which performs as a bus as shown in FIG. 2h of the patent. Layer 218 is then removed in a differential etch process (FIG. 2i of the patent) which however creates the risk of contaminating the Ni-Au contacts. The present invention seeks to address this disadvantage.
A process according to the invention addresses the growing need for applying stable electroplating met hodologies to very dense circuit designs. The method of the invention incorporates a selective laser ablation step and a structure that can be processed in a manner entirely consistent with existing printed circuit board manufacturing requirements. Electrical performance of the circuit is enhanced by not only the novel structure, but also by the ability to incorporate greater circuit densities and isolation lines. The technique is particularly useful in IC packaging applications including ball grid, land grid, or pin grid array formats, but can also be customized to suit a variety of end user applications such as circuit boards.
According to one aspect of the invention, a method for electroplating a substrate with a circuit pattern includes the steps of:
forming a number of electrical circuits on a substrate, which circuits include an electrically conductive bus that interconnects the circuits;
covering the electrical circuits with a soldermask, leaving electrical contact portions exposed;
electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish; and
then severing the bus at locations between circuits so that the circuits are electrically isolated from each other.
A circuit board made according to this process will bear the remnant of the electrically conductive shorting bus, generally a closed path or ring intersecting each of the circuits that has been severed at a location between each circuit. Otherwise the circuit will generally resemble known circuit boards or integrated circuit substrates. The severing operation can be carried out using a precision laser to either cut the electrically conductive shorting portion directly, or cut a soldermask layer over it so that exposed portions of the electrically conductive shorting portion can be removed by chemical etching. Where nickel-gold is used as the contact surface finish, the method of the invention can reduce gold consumption up to 70%.
According to a further aspect of the invention, a process of forming an integrated circuit package, includes steps of:
forming a dielectric layer on one surface of a substrate;
forming a number of electrical circuits on the dielectric layer, which circuits include an electrically conductive bus that interconnects the circuits;
covering the electrical circuits with a soldermask, leaving electrical contact portions exposed;
electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish;
severing the bus at locations between circuits so that the circuits are electrically isolated from each other;
mounting an integrated circuit die on the substrate; and
connecting the integrated circuit die to the surface finish of the electrical contacts.
The substrate and circuits are generally made of copper in such an IC package, whereas the preferred surface finish is successive layers of nickel and gold.
A circuit board according to the invention includes a substrate such as a copper plate or other substrates conventionally used to make circuit boards, a dielectric layer formed on a surface of the substrate, a number of electrical circuits formed on the dielectric layer, which circuits include an electrically conductive bus that interconnected the circuits, which bus has been severed forming cuts at locations sufficient to electrically isolate the electrical circuits from one another, and a soldermask covering the electrical circuits but leaving electrical contact portions thereof exposed, the contact portions having a surface finish deposited thereon. These and other aspects of the invention are described further in the detailed description that follows.